Who we are

Integral is building technologies to treat neurological and psychiatric disorders.

Our first device is a miniaturized, implanted, deep-brain interface for severely affected patients. It will have unprecedented capabilities for recording and modulating neural activity and for monitoring patients’ symptoms.

This device will dramatically advance our ability to treat brain disorders and to understand their biological causes. We will use this unique discovery platform to develop an expanding range of more effective treatments that will ultimately be accessible to everyone.

Leadership:

• Flip Sabes, CSO - Neuralink cofounder, UCSF Professor Emeritus, neuroscientist and neurotech innovator

• Milan Cvitkovic, CEO - Neurotech venture builder; previously first-hire at Convergent Research, AI researcher, and software engineer

• Stephen O'Driscoll, VP of Engineering - Verily cofounder and former Head of Electrical Engineering, former Director of Device Electronics at Science Corp

We prioritize ambitious engineering, speed, and patients' needs.

What you’ll do

You’ll be a founding member of Integral's ASIC team, responsible for developing - from scratch - and shipping the core ICs that will define the capabilities of our first product.

You'll build chips for neural recording and stimulation that achieve state-of-the-art miniaturization, power efficiency, and channel count, designed to meet the highest standards of reliability, safety, and supply chain resilience. More specifically, you'll be responsible for ultra-low-power custom cores for real-time processing, clock and data communication interfaces, and top-level integration.

We work full-time, in-person in South San Francisco.

Who we’re looking for

You should have substantial skills and expertise across most of the following:

• RTL design concepts and implementation via Verilog

• Logic synthesis techniques to optimize RTL code, performance, and power; especially low-power design techniques

• Static timing analysis (STA) and formal verification tools and methodologies, e.g. UVM

• DFT flow (SCAN/IDDQ/MBIST)

• Multiple clocks, synchronous and asynchronous

• Scripting languages like Python

• Buses, intra- and inter-chip data interfaces, including drivers, receivers, and SerDes for interchip communication

Experience with any of the following would be a bonus:

• Mixed-signal integration and top-level chip simulation 

• Power-constrained, battery-operated devices

• Equalization for wireline communications e.g. predistortion, DFEs

• FPGAs and emulation platforms

• Development of ATE patterns for digital and mixed-signal designs, and support of ATE activity including test pattern debug and test-time reduction

• Physical design

• Chips for heavily regulated industries

Neurotechnology experience is not necessary. A track record of swift execution is.